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7/2/2025, 9:41:35 PM
>>63928143
>you can compensate with a bigger die (more transistors)
Yeah sure, but unless you want to put 2000 trivial microcontroller tier cores on that die, someone has to design and validate a more complex core.
RISC-V is far less of a mess than x86, but a high performance core's still going to want pipelining, superscalar + speculative execution, branch prediction, etc. and getting all that to work reliably is probably a lot of work.
Picrel is one of the better Chinese x86-64 cores out there. Perf somewhere on the level of an AMD Bulldozer from 2011 (so not that fast).
There's a lot of tiny implementation detail inside each box that gets refined over CPU generations; I think most RISC-V cores are just at the start of that process.
>you can compensate with a bigger die (more transistors)
Yeah sure, but unless you want to put 2000 trivial microcontroller tier cores on that die, someone has to design and validate a more complex core.
RISC-V is far less of a mess than x86, but a high performance core's still going to want pipelining, superscalar + speculative execution, branch prediction, etc. and getting all that to work reliably is probably a lot of work.
Picrel is one of the better Chinese x86-64 cores out there. Perf somewhere on the level of an AMD Bulldozer from 2011 (so not that fast).
There's a lot of tiny implementation detail inside each box that gets refined over CPU generations; I think most RISC-V cores are just at the start of that process.
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