>>106909512
Arrow Lake has a good memory controller, but it's part of the SoC tile.
There's a latency penalty when the memory controller has to work with the CPU cores that are on a separate tile.
The faster the memory speed, the better for Arrow Lake.
These chips are basically starting at a +20ns (or higher) memory latency penalty.

Most Z890 boards should support 8000MT/s speeds. Go higher if you buy a 2-DIMM slot board, but the platform value from the CPU discount evaporates.

>>106282451
>but the other part is hoping the core ultra will be super cheap
The packaging requirement for the disaggregated tiles sets a higher price floor.
Plus, TSMC is overcharging Intel for the core & GPU tiles.

>>105854247
Don't get your hopes up for gaming.
Nova Lake might not even catch up to the 9800X3D, let alone Zen 6.

>>105566093
Doubt it, the media & display engines are on a separate tile.
That SoC tile is using a cheaper TSMC 6nm node iirc.
The Celestial cores are at least on TSMC 3nm.

Intel is not ready to sell a Druid dGPU.