>>105730195post zentimings
this thread has accumulated a lot of useful information, go through some of the earlier posts
>>105730197>I'm confused... that's literally what i saidyeah just making sure, a lot of people don't understand that timings are measured in clock cycles
>and you are telling me the performance is about equalperformance is better
you're overclocking the memory controller and IF as well
going from 3200 with XMP timings to 3200 with tight timings gets me 14%
going from 3200 to 3733 with equal absolute timings gets me another 7%
(only one test, but a real world scenario)
but you're already in diminishing returns territory, if you're happy with the performance already stick to 3000C15
>I honestly doubt that could be enough to bring me to a stable 3200 with decent timingsyou'd be surprised
with default drive strengths i can't run 3600 XMP stable on this board
with "fixed" drive strengths booting and stress testing up to 4066 is no problem (infinity fabric completely gives up after that point)
>doesn't lower timing/lower frequency on average require more vSoC/vdimm than higher timing/higher frequency?VDIMM yes
VSOC no, you need more voltage specifically to run higher UCLK and FCLK
for low idle power you want low memory frequency with tight timings (what you're doing right now)
i think you already have something good figured out for your usecase (low idle power and weird memory setup) so don't worry about it too much
>>105730223you're close to the limit so any change you make is for aesthetic/tinkering purposes
that's B-die so tRFC could be a lot lower
tCL will go lower with more VDIMM
tRC might go lower
tRRDL could be 4
tWTRL could be 8
SCLs might do 2/2 or 3/3
if those are 4 DIMMs RDRDSD/RDRDDD should be 4 and WRWRSD/WRWRDD should be 6