i'm trying to prevent an op amp output and a latching comparator output from fighting one another. see pic related and pretend that input offset doesn't exist and that a viable SR latch output is following the LM339. both the LM358 and LM339 latching output are +12V single supply. when an over-current event is detected i want the MOSFET gate latched to 0V but the comparator and i don't want the op amp to fight it.

how can i prevent this?

>latch power-down the LM358
is this viable? i read conflicting things about powered down op amps and undefined or unexpected behavior, but it wasn't specific to the LM358.

>analog SPST in the op amp output path
briefly looked into this but cheap analog switches have fucking awful performance? CD4066 as an example has 125 ohm @ 25 C on resistance at 15V supply, with a recommended maximum of 10 mA source/sink. considering the LM358 is feeding into a capacitive load (NMOS gate) this would make the problem even worse.

>your circuit is retarded
i'm trying to build a 2-in-1 battery charger and electronic load. the NMOS is dual purpose: variable resistor element for discharge and power path switch for charge termination (over voltage, over current, over temperature, etc.). yes, the NMOS will be DC SOA rated.