>>720695373
Hi,
I'm experiencing issues with the ACID 800 test suite when using the latest MiSTer FPGA core and the ReVerSE-U16 core adapted for the Tang Nano 20K. In particular, the following tests are failing:
DLI timing: Incorrect instruction count after WSYNC-delayed DLI: 2 != 1
POKEY Timer timing: 1.79 MHz 8-bit timer fired too late after 23c change (>44c)
POKEY Init timing: 15 kHz IRQ fired too late after exiting init mode
Have these issues already been addressed?
Regarding the first error, I'm wondering whether the timing in ANTIC.vhdl is accurate — especially this part:
wsync_delay : entity work.latch_delay_line
generic map (COUNT => 1)
port map (
clk => clk,
sync_reset => '0',
data_in => wsync_write,
enable => antic_enable_179,
reset_n => reset_n,
data_out => wsync_delayed_write
);
This delay seems questionable, as the original Atari hardware halts the CPU immediately upon WSYNC (after the current instruction cycle completes), without any extra delay. When I remove the delay in the code, the test passes — but of course, this breaks other timings.
I'm curious if you've already looked into this, or have any insights.
Issues with certain demos (e.g. Alley Dog) have been reported elsewhere and could potentially be related to the same ANTIC timing inaccuracies.
Best regards,
Chris
